1. Field of the Invention
The invention relates in general to the field of logic circuits, and, more particularly, to logic circuits used in computer systems. Specifically, the invention relates to a predriver logic circuit to improve the output characteristics of a driver circuit for a bus.
2. Description of the Related Art
Modem computer systems may contain several microprocessors, micro-controllers, and other digital devices connected to each other by a bus. The bus transports data among the microprocessors and other components and is composed of a number of traces. Traces are wire-like connections that are printed on a circuit board and function as transmission lines.
In most modem computer systems, data is in the form of bits (i.e., binary digits). Bits are typically represented as voltages. When positive logic is used, a bit value of one (i.e., a logic one) is generally represented as a high voltage, while a bit value of zero (i.e., a logic zero) is generally represented as a low voltage. A high voltage, as defined in this application, is a voltage substantially equal to a supply voltage V.sub.CC when used "on chip" and a supply voltage V.sub.DDQ when used for the input/output circuits. A low voltage is a voltage level substantially equal to a ground voltage V.sub.SS.
FIG. 1 is an equivalent circuit representation of a transmission line 100, which may be used to send information from one location to another. Generally, current is sent from one location along a top rail 103 to a second location, and return current is sent back to the first location along a bottom rail 104. Associated with the rails 103, 104 are several inductors 107 and capacitors 108, which constitute an ideal transmission line having impedance Z.sub.O.
One skilled in the art will appreciate that as current flows along the top rail 103, it encounters an inductor with a current-to-voltage relation defined as ##EQU1## where i is the current through the inductor and V is the voltage across it. This relation indicates that the current flowing through an inductor varies as time varies. Thus, as current flows through the inductor 107, a voltage forms across the inductor 107 and may be stored on a corresponding capacitor 108. As the current continues to progress down the transmission line 100, data is continually stored as voltages on corresponding capacitors 108. In this manner, data may be sent from one location to another.
FIG. 2 illustrates a stylized representation of a conventional driver circuit configuration for a bus that has a transmission line 200. A driver circuit 205 is coupled to the transmission line 200 and a predriver circuit 210. Within the driver circuit 205, there are at least two devices that function essentially as switches 215, 220 and are used to connect the transmission line 200 to the voltage supplies 225, 230. These devices generally have terminals that allow the position of the switches 215, 220 to change and are connected to the predriver circuit 210 by the lines 235, 240, respectively. The switches 215, 220 are typically implemented using NMOS and PMOS devices with an associated resistance. The output resistance associated with the switches 215, 220 is equal to the sum of the resistance of the resistors 216, 221.
The input lines 226, 231 of the predriver circuit 210 may be used to generate signals on the lines 235, 240. An enable input signal may be applied to the line 226, while a data signal may be applied to the line 231. One skilled in the art will appreciate that when the enable line 226 is active, data may be passed from the predriver circuit 210 to the driver circuit 205 on one of the lines 235, 240. In this case, the corresponding switch (e.g., switch 215) would close enabling the data signal to be applied to the transmission line 200. During data transitions, the switches 215, 220 may be closed at the same time, momentarily. When the enable line 226 is not active, the switches 215 and 220 are open, leaving the transmission line 200 undriven (i.e., a signal is not being applied to the transmission line). Because the predriver circuit 210 controls the opening/closing of the switches 215, 220, it affects the application of signals to the transmission line 200.
When the transmission line 200 is connected to one of the voltage sources 225, 230, the transmission line is being "driven" by the driver circuit 205. Associated with the driving of the transmission line 100 is the charging time of the predriver output lines 235, 240. The charging time, as defined in this application, is the length of time needed for the voltage applied to the lines 235, 240 to reach a maximum state voltage. For example, the charge time would be the time that it takes for the voltage at the terminal to reach the voltage V.sub.CC if a logic one is being applied to the line 240. The lines 235, 240 are generally charged at an exponential (i.e., RC) charge rate. A very fast RC charge rate behaves similarly to a linear charge rate while the exponential nature is more evident with a slow RC charge rate. One skilled in the art will appreciate that charge rate may refer either to the rate of charging or discharging and will be used in both cases.
If a fast RC charge rate is chosen, the driver circuit 205 is charged extremely fast, which may result in simultaneous switching output noise (i.e., ground bounce). Ground bounce is generally defined in the art as a variation in the ground voltage that occurs when the signals on multiple transmission lines transition from one logic state to another logic state, generating large changes in current over a short period of time (i.e., instantaneous current). Typically, a ground parasitic inductor is connected between a switching device and the ground voltage supply. As previously mentioned, current through an inductor varies with time, which causes a voltage to be present across the inductor. The voltage across the inductor becomes larger as more instantaneous current is routed to the ground supply from multiple transmission lines. Ground bounce generally causes additional propagation delays in the output signal thereby reducing the timing margin at the receiver. Distortion in the shape of the signal may also result from ground bounce.
Alternatively, the predriver circuit 210 may charge the lines 235, 240 at a slow RC charge rate. This charging rate charges these lines fast initially, and later slowly, at an exponential charge rate, which may cause the final voltage level to vary depending on the type of data pattern. For a sustained data stream (e.g., 1-1-1-1), the predriver circuit 210 is generally unable to charge the lines to a rail voltage level (e.g., V.sub.CC). Data transfer generally involves the transfer of a combination of "ones" and "zeroes" to a single transmission line, which is referred to as a data pattern.
Typically, there are two types of data patterns. A high-frequency data pattern generally oscillates (i.e., the voltage level toggles between two values) every clock cycle. For example, a data pattern such as 1-0-1-0-1-0 is a high-frequency data pattern, assuming that the signals are generated at each clock transition. The voltage level of that data pattern toggles between high and low logic states every clock transition. In contrast, a low-frequency data pattern is generally defined as a data pattern that does not transition at every clock transition (e.g., 1-1-0-0-1-1-0-0). During slow RC charging, one state in a high-frequency pattern charges to a voltage level different from the same state in a low-frequency pattern, as will be discussed in greater detail below.
FIG. 3 is a timing diagram illustrating how the output voltage for a predriver circuit varies with time for fast and slow RC charge rates. The signal 300 illustrates the variation of the output voltage for a fast RC charge rate. In the region labeled 305 corresponding to a first bit cell, the voltage quickly reaches the maximum state voltage (e.g., V.sub.CC) and remains at that voltage for the remaining time in the bit cell. A bit cell, as defined in this application, is the period of time in which one data bit is valid. The signal 300 illustrates similar behavior for the regions labeled 306 and 307.
A slow RC charge rate generates the signal 302. Within the region 305, this signal charges to a voltage V.sub.1, while within the region 307, this signal charges to a considerably larger voltage level V.sub.2, indicating data pattern dependent charging. One skilled in the art will appreciate that the region 307 actually consists of two consecutive bit cells that correspond to two logic ones. Thus, FIG. 3 illustrates that a 1-0-1-1 data pattern would charge to a different voltage level than a 1-0-1-0 data pattern. The charging to different voltage levels for the same state may cause the driver circuit to behave differently (e.g., the line may take longer to settle). This aberrant behavior may vary the timing requirements for proper operation and affect signal quality.
Conventional predriver circuits generally charge the select terminals of the driver circuit at a rate between the fast and slow RC charge rates. The amount of ground bounce and data pattern dependent charging may be reduced by varying the driver edge rate (i.e., the change in voltage with time) to match the stub length in a bus. The voltage variation for this rate is shown as the signal 303 in FIG. 3. Though the ground bounce at this rate is considerably lower, the ground bounce is still present and may lead to false logic signals. Similarly, though the amount of data pattern dependent charging is considerably lower, it is still present, which may impact signal quality, among other things. Thus, it would be beneficial to have a predriver logic circuit that is capable of overcoming the shortcomings of conventional predriver logic circuits.